Fast TRD Pre-Amplifier Shaper for the CBM experiment

In order to achieve an overall noise of less than 1000 electrons per channel for a typical input capacitance of a total of 5-10 pF, the use of a low-noise circuit is required. A well proven topology to fulfil such a requirement is shown in fig. 1. Each channel consist of a low noise chargesensitive amplifier, an active CR-(RC) pulse shaper. The main noise contributor is the input transistor of the preamplifier that is based on the folded cascode topology. The cascode consist of a common-source stage followed by a common-gate stage. It combines two transistors (a wide input transistor and a narrower cascode transistor) to obtain: i) high transconductance and low noise of a wide transistor, ii) high output resistance and low output capacitance of a narrow transistor, and iii) reduced capacitance between output and input. In addition a Pole-Zero network is included to avoid undershoot that will strongly limit the counting rate behaviour. In the design a MOS transistor (MF) is used with a feedback capacitance Cf that is continously discharged with a decay time td = Cf · Rds (MF). This continuously sensitive design is particularly suitable for a detector with high occupancy and high counting rate. A typical impulse response is shown in fig. 2. In this first prototype the peaking time is 70 ns (t0/100), and the FWHM is about 70 ns. In terms of noise this circuit fulfil the requirement with an ENC of less than 400 electrons for an input capacitance of 10 pF. In terms of power consumption the circuit uses 16 mW/channel. The chip is fabricated in 0.35 μm standard CMOS technology, and it has a pad pitch of 200 μm and a total area of 12 mm. A first prototype using this design was submitted in October 2005 and it has just been received from the foundry. The first tests in lab and in test beam show that the chip responds according to specifications, in particular with very Figure 2: Typical impulse response of the fast PASA done in 0.35μm technology